Memory devices are typically assembled into memory modules that are used in a computer system. These memory modules typically include single in-line memory modules (SIMMs) having memory devices on one side of the memory module, and dual in-line memory modules (DIMMs) having memory devices on both sides of the memory module. The memory devices of a memory module are accessed in groups. Each of the groups are commonly referred to as “ranks,” with single-sided DIMMs typically having one rank of memory devices and double-sided DIMMs having two ranks of memory devices, one rank on either side of the memory module.
Each of the memory devices of a memory module receives a set of signals which is generated by a memory controller to command the memory devices to perform various memory operations. For example, these signals include a clock signal for synchronizing the timing of the memory operations with the memory controller, command signals to direct the memory devices to perform specific memory operations, and address signals to identify a memory location in the memory devices. Additionally, the memory controller can send write data signals for data that are written to the memory device, and write strobe signals for signaling to the memory device the time at which write data is provided to the memory devices by the memory controller. The memory controller also receives signals from the memory devices of a memory module, such as read data signals for data that are retrieved from the memory devices and read strobe signals for signaling to the controller the time at which read data are provided to the memory controller by the memory devices.
As the clock frequencies increase for the memory systems in which the memory devices and memory modules operate, timing and voltage margins for the various signals related to memory device operation become more critical. Subtle variations in signal timing and operating conditions can negatively impact memory device performance. Consequently, it is desirable to improve timing and voltage margins without sacrificing performance, where possible.
An example of an approach to improving timing and voltage margins is the use of on-die terminations (ODT) for input/output buffers, such as data strobe, data, and data mask buffers of the memory devices. The ODT circuits provide resistive terminations that improve voltage margin and signal integrity for both read and write operations. The improved voltage margin also indirectly provides improved timing margin in that the time for which data is valid is increased with the use of ODT. As a result, the “data eye” for memory devices having ODT are generally larger than for memory devices without ODT, which enable systems having these memory devices to attain higher data rates.
The ODT for conventional memory devices are typically enabled and disabled for a memory device using an ODT control signal provided to the memory devices by a memory controller. With the ODT control signal active, the ODT for the data strobe buffers, the data buffers, and the data mask buffers are enabled to provide resistive termination, and with the ODT control signal inactive, the ODT for all of the buffers are disabled. Thus, the ODT control signal can be used by the memory controller to turn the ODT of a rank of memory on and off as needed. For example, in a memory module having a single rank of memory devices, the ODT is typically enabled for write operations, but disabled for read operations. Having control over the activation of the ODT of the rank of memory devices also allows for a preferred operating condition for writing data to a rank of memory devices in a memory system having at least two ranks of memory devices. The preferred condition is to disable the ODT for the rank of memory devices of the memory module to which data is being written and enable the ODT for the rank of memory devices of the memory module to which data is not being written. Thus, to setup this condition, the memory controller provides an active ODT control signal to the rank of memory devices not being accessed and an inactive ODT control signal to the rank of memory devices being accessed.
Another approach to improving signal timing margins is to calibrate the timing of various signals between a memory controller and the memory devices of a memory system. The signals that are received and provided by the memory controller and the memory devices of the memory module are coupled to signal lines that extend between the memory controller and the memory devices. Some signals are provided and received in parallel by each of the memory devices of the memory module and the memory controller over respective sets of parallel signals lines. These type of signals include data signals (both read and write) and strobe signals (both read and write). Each of the memory devices, at least for one rank, receives and provides data and strobe signals over its own set of signal lines that are coupled to the memory controller. In contrast, other signals are provided using a common signal line. For example, a clock signal provided by the memory controller to the memory devices of a memory module having a “fly-back” arrangement share a common clock signal line to which each of the memory devices are coupled.
In laying out the signal lines of a memory module that are coupled to the memory controller and the memory devices, it is generally the case that many of the signal lines will have different lengths. These different lengths can cause timing skews between the signals that are provided in parallel to the memory devices and the memory controller, such as data signals and strobe signals. As a result, data being written to the memory devices can arrive to each of the memory devices at slightly different times although the data is coupled to the respective signal lines by the memory controller simultaneously. Similarly, read data from each of the memory devices of a memory module can arrive at the memory controller at slightly different times although the memory devices couple the respective read data to the signal lines simultaneously.
Additionally, due to propagation delays of a signal line, a time difference at which a signal is received along the length of the signal line will result. Thus, a signal, such as a clock signal, that is provided to the memory devices of a memory module over a shared signal line will be received by each of the memory devices at slightly different times, depending on where along the length of the signal line the respective memory device is coupled.
These timing skews that are created between signals and over the length of a signal line may be only several picoseconds long. However, in high-speed memory systems, several picoseconds can significantly reduce the timing margin of signals. As the timing margin of signals decreases, subtle timing variations caused by other factors, such as variations and drifts in power, voltage, and temperature, may result in memory errors. Moreover, the timing of the signals provided to the memory devices by the memory controller can be skewed relative to one another because of the length of the signal lines and the manner in which the signal is provided to the memory devices. For example, it is desirable for write strobe signals to be aligned with the clock signal as received by each of the memory devices. However, as previously mentioned, the strobe signals are typically provided to each of the memory devices on parallel sets of signal lines, whereas the clock signal is provided to each memory device on a common signal line. In this arrangement, the relative timing of the clock signal and the write strobe signal for each of the memory devices may be different due to the propagation delay of the clock signal on the common signal line. That is, not only are the write strobe signals be skewed from the clock signal, it is possible for the amount of timing skew to be different for each of the memory devices. As a result, the timing margin for signals may be further reduced by the timing skew of the different types of signals provided to the memory devices on signal lines having different arrangements.
An approach to addressing the problems of reduced timing margin due to timing skew between signals and between the memory devices of a memory module is to calibrate the relative timing of the signals to each of the memory devices in order to compensate for the timing differences. “Pre-skewing” the timing of signals, for example, by selectively delaying the time at which the respective signals are provided by the memory controller to each of the respective memory devices, can compensate for the timing skew inherent in the memory system. Additionally, periodically performing calibration can be used to compensate for timing drift.
A specific proposal for write data strobe to clock calibration for the ranks of memory devices of a memory system has been proposed. In performing the “write levelization,” a memory controller provides the clock signal and a write strobe to each of the memory devices of a rank. The memory devices are each equipped with a SR-latch having the clock signal applied to a set-input and clocked by the respective write strobe signal. The output signal of the SR-latch is provided back to the memory controller as a data signal, which is then used by the memory controller to adjust a time delay for when the write strobe is provided to the rank of memory devices. In this manner, the delay can be adjusted until the write strobe and the clock signal are aligned, as received by the respective memory devices of a rank of memory.
In practicing the write levelization process with conventional memory devices, a problem results for memory systems having more than one rank of memory devices. As previously discussed, the preferred operating condition for performing a write operation to a rank of memory devices is to disable the ODT for the rank of memory devices being accessed and enable the ODT for the rank of memory devices not being accessed. Typically, an inactive ODT control signal is provided to the rank of memory devices being accessed to disable the ODT for the data strobe, data, and data mask buffers, and an active ODT control signal is provided to the rank of memory devices not being accessed to enable the ODT for the data strobe, data, and data mask buffers. As previously discussed, the write levelization process requires, however, that a write strobe signal is provided to the memory device to clock a SR-latch, and the output of the SR-latch is provided back to the memory controller, preferably, as a data signal. To accurately simulate write operating conditions, and consequently obtain accurate write levelization, the ODT for the data strobe buffer of the rank of memory devices not being accessed should be enabled, while the ODT for the data buffer for the same rank of memory devices should be disabled to provide the SR-latch output signal back to the memory controller. This preferred condition cannot be set using conventional memory devices having ODT because although the ODT for a memory device can be enabled and disabled using the ODT control signal, the ODT for the data strobe, data, and data mask buffers are enabled and disabled together. Thus, the ODT for the data strobe buffers cannot be enabled while the ODT for the data buffers are disabled, and vice-versa.